The present invention relates to a vector mask operation control unit for use in a data processing system to execute masked vector instruction processing.
For a conventional data processing system of this kind, reference may be made to the specification of the U.S. patent application No. 544,674/1983 (corresponding to the Japanese Patent Disclosure No. 103482/1985) filed on July 20, 1984 by International Business Machines Corporation. The system disclosed by this patent has a central processing unit and a vector processing unit. In this system, mask bits merely control setting into the vector register and restraint on storage into the main memory, but do not control the reading operation for unrequired operand data or inhibition of arithmetic operations. To control this reading operation for the unrequired operand data and the inhibition of arithmetic operations, this system has to multiply, at the time of address generation of operand data, the number of elements (N) whose arithmetic, loading or storing operations are inhibited by the address of the distance between vector elements (V.sub.I), that is, the vector-address-increment (VAI) value, and thereby to generate an operand address increment (NXV.sub.I) A multiplier to be used for this multiplication, however, requires a considerable amount of hardware.